2023-32070 – Design Architect Front-End / Junior IP engineer M/F

  • CDI
  • N’importe où
  • Publié il y a 2 mois

Regular/Temporary : Regular
Position description :
STMicroelectronics (STM) business supports leading edge system companies very successful in optical, wired and wireless infrastructures by providing complete design platforms and production capabilities for very high end SoC (System On Chip) / ASIC (Application Specific Integrated Circuit) in advanced FinFet Technologies (7, 5 and 3 nm nodes).
For these SoC/ASICs the availability of pre-defined functional blocks, silicon validated and complying with specific market defined standard – named “Intellectual Properties” (IP) – represents one of the smartest ways to exploit latest FinFet technologies nodes extreme integration capabilities allowing STM customers to enrich their SoC with many new functionalities enabling new markets or new products w/o affecting overall time to market and/or R&D development cost.
In this complex context, STM for wireless and optical infrastructure ASIC business is expanding R&D organization opening a new position for a junior IP engineer who will be part of our IP management team.
The IP engineer supports the adoption of different IPs including CPUs, high-speed interfaces such as consumer PCIe-USB / High Speed Serdes – Ethernet / Memory interfaces (DDR, LPDDR) within the SoC/ASIC design team all the way from early definition down to silicon validation with the following activities
– Overviewing IP providers offer and contributing to the IP eco system roadmap for SoC/ ASIC development
– Analyzing SoC requirements with IP features, capabilities and compliancy with the required standards (Jedec and international committee)
– Supporting SoC technical presales by delivering key data such as PPA (Poer Performance Area)figures
– Supporting STM central IP source office during the IP licensing
– Support the SoC/ASIC team covering all design/ verification/ implementation flow
– Support silicon validation and production test preparation with FW/SW/ Debugging activities
– Supporting device maturity process
This person will be interacting with many STM internal and IP providers external teams making his/her role very visible and fast growing in our organization.

Candite’s skills shall cover:
– “Learn and deliver” attitude, understanding problems and deliver solutions is key;
– Strong teamwork and multicultural attitude. No solo, team matter;
– Willingness to get challenged. Our SoC are always using all the latest technologies/ solutions available in the market;
– Good university knowledge of SoC design flow/ semiconductor process /FW/SW.
Education level required : 5 – Master degree
Language / Level :
English : 2- Business fluent
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