Regular/Temporary : Regular
Position description :
Part of Technology R&D, ‘Test Vehicle Engineering’ department is in charge of the design, test and stress of the circuits (test-chips) required for the qualification of the ‘Technology Platforms’ (TP). More specifically, SDA team is analyzing silicon data to conclude on the qualification of these TPs and the digital IPs (standard cells, memories, etc.) part of them.
Within SDA team, and based in ST Crolles in multi-cultural environment, you will be in charge of the analysis of the silicon data from the test-chips. The job will cover several aspects:
Specification of circuit and test
Analysis of silicon data and understanding of the gaps
Correlation between silicon data and spice models for Cmos logic, in tight collaboration with modeling team
Drive debugging activities when needed.
After review with all stakeholders, build reports required for TP and IP qualification.
This activity will allow to acquire large set of skills thanks to the interactions with several teams in TRD: design, test, modeling, process. In this job, initiative and proposals for improvement of the methodology are very welcome.
Good knowledge of the operation of CMOS devices (mosfets) & circuits (basic logic circuits, memories, …)
Good interpersonal skills, teamwork
Problem solving methods.
Fluent English (all written and most oral comm is in English)
Previous experience in one or more of the following areas will be added value:
Design of CMOS cell libraries (memories, stdcells, …)
Circuit design (full-custom or semi-custom)
Electrical test, failure analysis
Education level required : 5 – Master degree
Language / Level :
English : 2- Business fluent
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