Regular/Temporary : Regular
Position description :
•Work through all phases of physical design of high performance PHY design from Synthesis to delivery GDSII.
The responsibilities include but are not limited to:
•Generate block/chip level static timing constraints.
•Build full chip floor-plan including pin placement, partitions and power grid.
•Develop and validate high performance low power clock network guidelines.
•Perform block level place and route and close the design to meet timing, area and power constraints.
•Generate and Implement ECOs to fix timing, noise and EM IR violations.
•Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers.
•Participate in establishing CAD and physical design methodologies for accurate by construction designs.
Experience of 6+ years in state-of-the art of Physical Design experience on high PHY and/or SOC designs
Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route
Significant working experience in developing and implementing Power-grid and Clock specifications
Deep Understanding of all aspects of Physical construction, Integration and Physical Verification
Deep knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes.
Power user of industry standard Physical Design & Synthesis tools
Shown understanding of scripting languages such as Perl/Tcl
Extensive knowledge of Extraction and STA methodology and tools
Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
Education level required : 5 – Master degree
Language / Level :
English : 2- Business fluent