2022-23924 – Senior Digital Verification Engineer M/F

  • CDI
  • N’importe où
  • Publié il y a 6 mois

Regular/Temporary : Regular
Position description :
The purpose of this job is to guarantee specification compliancy of the digital design by means of verification methodology and concepts. It supports the definition and enhancement of state-of-the art methodologies serving as clear verification sign-off criteria for tape out.
Verification planning, maintenance, feature extraction, verification test case development and regression testing setup
Develop and Implement verification IP
Initiate review meetings with design/verification engineers
The Employment search is addressed to candidates of both genders, under Law 10.04.1991 n. 125, as amended by Legislative Decree n. 198/2006 which guarantees gender equality at work.

Experience 6+ years in state-of-the art verification methodologies owning the verification of SoCs
System Verilog for verification using advanced verification methodologies (preferably OVM/UVM or similar)
Assertions based verification
Constraint random driven verification
Fluent in either Verilog or VHDL RTL coding and ASIC design methodology
Concise and proactive communication skills within a multi-side and multi-cultural environment
Ability to persuade and influence based on technical facts
Takes responsibility for solutions and makes them happen, self-motivated
Team leader experience
The requirement in term of skills are:
Solid knowledge on systemverilog UVM methodology, SVA assertions
Experience on Cadence Design flow (xcelium, Vmanager,..)
Experience on RTL and Gate Level debugging
Education level required : 5 – Master degree
Language / Level :
English : 2- Business fluent
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