Regular/Temporary : Regular
Position description :
You will be in charge of analog and mixt analog-digital IP design solution definition from electrical specification. You will be in charge of the design solution validation at CAD level to insure IP area and electrical performances alignement to user manual. The designed IPs will be then qualified on silicon.
You will be evolving in an analog design team in charge of power management and One Time Programmable memories IPs development for several CMOS technology nodes from 0.25um to 18nm nodes.
Analog design (sense amplifiers, charge pumps regulators).
Memory design and architecture.
CMOS technology knowledge.
Education level required : 5 – Master degree
Language / Level :
English : 2- Business fluent
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