Regular/Temporary : Regular
Position description :
Drive to “zero-defect”. Responsibilities encompass the development of verification test bench, development of verification components, test case development for simulation, debugging failures and creating simulation cases for various studies. As an experienced professional, work with the cutting-edge verification methodologies on standalone IPs, Subsystem level and SoC level.
Responsibilities include but not limited:
Lead and manage complete SoC level Verification activities.
Verification planning & development, reviewing, architecture definition, Verification test bench development and implementation.
Development of verification test bench components such as drivers, monitors, response checkers as well as use most advanced UVM VIPs.
Development of direct and constrained-random stimulus for IP & SoC verification; Understanding and analysis of RTL code, functional, assertion coverage results;
Strong skills in debug, failure re-creation and root cause analysis
Gate level simulations (unit delay, and with SDF annotated) and its debugging
Test pattern debugging and testing for verification and automatic testers
Continuous improvement of verification methods/tools/flows/processes together with EDA partners. Finding cost effective and innovative verification techniques
Low Power intent verification using CPF, UPF will be desirable.
Assertion based verification will be a plus
Technical background/Key Skills:
VHDL/Verilog, System Verilog, C language and experience testbench development.
OVM/UVM, Class based verification methodologies.
Deep Understanding of multi core based SoC architecture
AMBA – AXI, AHB, APB bus protocols. ARM based subsystem.
NIC/FlexNOC interconnect with Cache coherency, PCIe/DDR3/LPDDR4/Flash memory subsystem architecture knowledge
Debug and trace architecture based ARM cores Eco-system
Communication Protocols like CAN, Graphics/Multimedia/Networking IPs like PCIe, MIPI, GPU, Ethernet, USB, DSP, Image/Computer Vision, RADAR processing
Experience in Safety and/or Security verification will be highly preferred.
Scripting proficiency – PERL, Python, UNIX/LINUX
Simulation tools like – Xcelium/VCS/Questasim. Planning and regression tools like VManager .
Exposure to safety verification, emulation platform will be preferred.
Exposure to any of defect and version management tool
Qualification: Bachelors/Masters in Electronics/Computer Science
Experience Required is from 4 years until 18 years
Location : Bangalore R&D Centre
Education level required : 4 – Bachelor degree
Language / Level :
English : 2- Business fluent
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