Regular/Temporary : Regular
Position description :
ST commitment to DEI – diversity, equity, and inclusion…..the TA team plan to launch an initiative for which we would like your views and further fine tune based on the feedback received during this session.
The 1st set of meeting we have conducted with our HR colleagues. Shared the concept and taken the feedback at HR level. Now, we would like to organize a session with our female colleagues working in our business departments.
As a part of SRAM Layout design team, you would be working on
1) Development of Memory Leafcell design as per the need of SRAM compiler architecture and Specifications
2) Stitching of memory leafcells to make a top level circuit abstraction
3) Verification of leafcells/circuit blocks including analysis of circuit behavior, timing marginalities, correct description of timing characterization intent on both pre and post layout netlist across the entire PVT space and compiler cut space.
4) Documentation and synthesis of results along with closure of all review actions.
Candidate must have a Bachelor or Master in Electronics with an excellent academic record. In-depth understanding of circuit fundamentals with a good academic exposure to digital and analog circuit design is a must. Any previous exposure to Memory design and characterization and associated CAD tools (Schematic editor, Spice Simulators, Characterization Infrastructure etc.) during academic curriculum or Industrial training would be an added advantage. Candidate must have good communication skills and ability to work efficiently in a team
Education level required : 4 – Bachelor degree
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