2021-15411 – Sr Technical leader/Sr SoC architect/ r Clock ,Power & Interconnect architect/Sr Digital IP designer M/F

  • CDI
  • N'importe où
  • Publié il y a 1 semaine

Regular/Temporary : Regular
Position description :
ST being an employer for diverse talent through employee testimonials and personal experiences; customizable spotlights that highlight important of diversity. ‘Return to work program’ help drive more equitable outcome for women professionals, who have taken breaks from the workplace for few years. The current opportunity is open to female candidates, who have taken career break between 1 to 5 years processes the relevant skills set as mentioned in this Job Description. ST commitment to DEI – diversity, equity, and inclusion.

Drive architecture/application teams in converging to an optimal specification from performance, design effort/cost point of view. This includes technical discussions on IP reuse, required interfaces and PPA optimization, deriving a balance between product features and time-to-market.
Build and develop system level knowledge in the team.
Be the SOC Technical lead and representative interfacing with IP/SOC architecture, IP/SOC design, Performance, post Silicon and platform teams. Work with above mentioned teams to define features, chip pervasive logic solutions and design/verification requirements.
Interface with the SOC design and verification teams to drive implementation and overall design QoR
Additionally, will be evaluating the need for new IPs, driving new protocol deployments as well as defining system wide guidelines for IPs to inter-operate together in the SoC. Be the primary SoC contact for complex problem resolution and forward-looking design initiatives.
Product/IP development flow compliance and adherence to quality processes.

Experienced about system applications, especially for what concerns performance analysis and tuning.
In depth understanding of system bus architectures (like AHB/AXI), including NOC and other interconnect technologies, with focus on performance/power optimization, bottlenecks identification, timing issues anticipation and resolution.
Competent on power and clocking architectural concepts, capable of driving their definitions and anticipate potential implementation issues.
Good knowledge of ARM cores, especially real time one like R52/Kite etc, to be able to drive product level PPA analysis, with solid understanding of system architectures, IO/pad-ring, and low power design.
Knowledgeable in complete implementation from SoC RTL to GDS, with good understanding of timing constraint definition targeting performance, area, and timing optimization.
Good exposure to complex mixed signal SoC development, including adequate understanding of high-speed interfaces like: PCIe, SGMII/RGMII, MIPI, DDR.
Automotive Safety ISO26262 knowledge is a plus.
Proven track record of leadership role in managing high level complex designs, driving and coordinating across different teams.
Good negotiator and able to manage tough situations.
Adaptability to different roles aligning with business needs, start-up attitude and able to balance resources, time constraints environment well.
Good communication and interpersonal skills.

Education level required : 4 – Bachelor degree

 
 
>>>> CLIQUEZ SUR CE LIEN POUR POSTULER A CETTE OFFRE D EMPLOI : SITE INTERNET



Détails Emploi Informatique & Web