Regular/Temporary : Regular
Position description :
We’re looking for a highly motivated & talented individual for Layout Design of Non Volatile Memories . Will member of team responsible for Macro development & their corresponding Testchips . Will also be performing Views generation & their verification for various NVM IP’s.
The team is deeply involved in Layout Design of Full custom Analog and Mixed Signal circuits for Non Volatile memories such as Op – Amps , Regulators , charge pumps Cells , Logic Circuits etc & their Testchips.
Expertise in EDA tools for Layout Design : Virtuoso , Calibre
Physical Design Verification ( DRC / LVS / RCX)
Experience on CMOS Layout Design
Good knowledge of fabrication process
Good knowledge of Perl / Tcl / Skill is preferred Proactive and self – motivated.
Good communication skills
Education level required : 4 – Bachelor degree
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